1. Field of the Invention
This invention relates to data-transfer interconnections for signal and data transfer between various IC devices, and more particularly, to a data-transfer interconnection for signal and data transfer between a CD-ROM (compact-disc read-only memory) decoder and its associated buffer memory, for example a DRAM (dynamic random-access memory). More specifically, the data-transfer interconnection of the invention allows a CD-ROM decoder having an 8-bit data bus to gain access to a 16-bit DRAM buffer memory by the incorporation of just one additional signal line between the CD-ROM decoder and the DRAM buffer memory.
2. Description of Related Art
A CD-ROM decoder is customarily coupled to a random access memory unit, usually referred to as buffer memory, for temporary storage of the decoded data. The size of the buffer memory significantly affect the overall performance of the CD-ROM drive. Conventionally, dynamic random access memory (DRAM) is used as the buffer memory for a CD-ROM decoder.
FIG. 1 is a schematic diagram showing the signal and data lines connected between the IC of an 8-bit CD-ROM decoder 17 and the IC of an 8-bit DRAM buffer memory 18. The signal/data lines includes an (n+1)-bit address bus 11 connected between the output address port ADDRESS on the CD-ROM decoder 17 and the input address ports A.sub.0 -A.sub.n on the DRAM buffer memory 18; a WE (write enable) signal line 12 connected between the output port WE on the CD-ROM decoder 17 and the input port WE on the DRAM buffer memory 18; an OE (output enable) signal line 13 connected between the output port OE on the CD-ROM decoder 17 and the input port OE on the DRAM buffer memory 18; a RAS (row-address strobe) signal line 14 connected between the output port RAS on the CD-ROM decoder 17 and the input port RAS on the DRAM buffer memory 18; a CAS (column-address strobe) signal line 15 connected between the output port CAS on the CD-ROM decoder 17 and the input port CAS on the DRAM buffer memory 18; and an 8-bit data bus 16 connected between the 8-bit parallel data I/O port DATA on the CD-ROM decoder 17 and the data I/O port DQ.sub.1-8 on the DRAM buffer memory 18. The WE, OE, RAS, and CAS signals are each a one-bit signal.
The foregoing data-transfer interconnection is devised for the 8-bit CD-ROM decoder 17 to gain access to the 8-bit DRAM buffer memory 18. It is also suitable for use on 4-bit DRAMs. However, when it is desired to expand the buffer memory to a 16-bit system the data bus 16 should be expanded also from 8-bit to 16-bit, which requires the data bus 16 to be also expanded to 16-bit. As a result, an additional 8 data lines are required. This will increase the number of pins on the IC of the CD-ROM decoder 17 by eight, thus increasing the manufacturing cost.
Presently, most CD-ROM drives are based on a decoder that is designed for use with 8-bit DRAMs. However, most of the DRAMs on the market are 16-bit or higher, and 8-bit DRAMs are not very widely available so their prices are higher than the 8-bit ones. The more costly 8-bit DRAMs are therefore required to be used with prior CD-ROM decoders.
One solution is to redesign the CD-ROM decoder to a 16-bit system that can use 16-bit DRAMs as the buffer memory. However, as mentioned earlier, this will require an additional 8 pins on the IC of the CD-ROM decoder, which causes the packaging cost of the IC of the CD-ROM decoder to be high.